The IKDB Bible

Credits

Memory Map

Interrupts

Internal Registers

Data Registers

16bit Timer

Serial Communication Interface

RAM Control

1 - Data Registers

There's four data registers, each bit of each data register can be set to
read or write by the associated control register:

• a bit 0 in the control register mean an input bit in the data register
• a bit 1 in the control register mean an output bit in the data register

For example, %11100000 in the control register mean:

• [0-4] : input bit
• [5-7] : output bit

If you read the data register, you will get only the values of bits [0-4].
If you write the data register, you will modify only the values of bits [5-7].

1.1 - Data Register 1

This register is mapped to the keyboard's matrix lines. (See keyboard table). The associated control register (DDR1) is set to all input (%00000000). (see DR3, DR4, keyboard handling)

1.2 - Data Register 2

• Bit 0 : Joystick 1 pin 5, output for selecting the 74LS244 (see DR4)
• Bit 1 : Left mouse button or joystick 0 Fire button.
• Bit 2 : Right mouse button or joystick 1 Fire button.
• Bit 3 : Acia TxDATA? (6301 receive)
• Bit 4 : Acia RxDATA? (6301 transmit)

1.3 - Data Register 3

Bits 1-7 are mapped to the first seven keyboard's matrix rows. (see keyboard
table).
The associated control register (DDR3) is set to all output (%11111111). (see DR1, DR4, keyboard handling)

1.4 - Data Register 4

Bits 0-7 are mapped to the next height keyboard's matrix rows. (see keyboard
table).
The associated control register (DDR4) is set to all output (%11111111). This register is also used to read joysticks directions, for this you need to select the 74LS244 by setting the bit 0 of DR2 to 0, on output, then turn the DDR4 to all input (%00000000). The four directions of each joystick are then readable on bits [0-3] and [4-7]. (see DR1, DR3, keyboard handling)

2 - SERIAL COMMUNICATION INTERFACE

The 6301 communicate with the ACIA trought the bits 3 and 4 of DR2. The SCI is made of four registers.

2.1 - RDR - Receive Data Register

This register contains the byte received from the ACIA. The bit 3 of TRCSR must be set to 0, to set the bit 3 of DR2 to input.
When a byte is received, the bit 7 of TRCSR is set, and a interrupt is fired if the bit 4 of TRCSR is set to 1.
The SCI can't receive more byte until you read TRCSR then RDR. It's mean next bytes are lost.

2.2 - TDR - Transmit Data Registers

This register contains the byte to be transimtted to the ACIA. The bit 1 of TRCSR must be set to 1, to set the bit 4 of DR2 to output.
Once the byte is transmitted, the bit 5 of TRCSR is set to 1, and a interrupt is fired if the bit 2 of TRCSR is set to 1.

2.3 - TRCSR - Transmit/Receive Control & Status Register

This register control the communications.

• Bit 0 (RW) : Wake Up, when set to 1, wait until ten 1 appears on the line, then it switch to zero.
• Bit 1 (RW) : Transmit Enable
• Bit 2 (RW) : Transmit Interrupt Enable
• Bit 3 (RW) : Receive Enable
• Bit 4 (RW) : Receive Interrupt Enable
• Bit 5 (RO) : Transmit Data Register Empty, is set to 1 when a byte have been sent, and is set to 0 when TRCSR is read then TDR is write.
• Bit 6 (RO) : Overrun or Framing Error, is set to 1 when a byte is received if the previous byte was not read, and is set to 0 when TRCSR then RDR are read.
• Bit 7 (RO) : Receive Data Register Full, is set to 1 when a byte have been received, and is set to zero when TRSCR then RDR are read.

2.4 - RMCR - Rate & Mode Control Register

The serial speed MUST be set to 7812.5 on ST.

Bits 0 and 1 control the serial speed:

• %00 : 62500 bits/s
• %01 : 7812.5 bits/s (ACIA compatible)
• %10 : 976.6 bits/s
• %11 : 244.1 bits/s

Bits 2 and 3 select the clock:

• %00 : Bi-Phase, Internal 4Mhz
• %01 : NRZ, Internal 4Mhz
• %10 : NRZ, Internal 4Mhz, DR2 bit 2 = clock ouput
• %11 : NRZ, External, DR2 bit 2 = clock inpout

3 - TIMER

The timer can generate interrupts. It's made of four registers.

3.1 - FRC - 16 bit Free Running Counter

This register is read-only.
This counter is incremented at each clock cycle (1mhz). When it reach $FFFF, the bit 5 of TCSR is set to 1, and the interrupt TOF is fired if the bit 2 of TCSR is set to 1. Then the value of the counter is set to 0.
After a reset, the value is set to 0.

3.2 - ICR - 16 bit Input Capture Register

This register is read-only.
It contains the value of FRC register at the last transition of the bit 0 of DR2. It computes the timing between two external events.
When the value of FRC is catched, the bit 7 of TCSR is set to 1, and an interrupt ICF is fired if the bit 4 of TCSR is set to 1.

3.3 - OCR - 16 bit Output Compare Register

When the value of FRC is equal to the value of OCR, the bit 6 of TCSR is set to 1 and an interrupt OCF is generated if the bit 3 of TSCR is set to 1. Also, the bit 0 of TCSR is sent to the bit 1 of DR2, if set to output.
After a reset, the value is set to $FFFF.

3.4 - TCSR - Timer Control & Status Register

• Bit 0 (RW) : Output Level, this bit is sent to bit 1 of DR2 (if set to ouput) when FRC reach the value of OCR.
• Bit 1 (RW) : Input Edge, if set to 1, the FRC is catched in the ICR on a up transition. If set to 0, on a down transition.
• Bit 2 (RW) : Enable Timer Overflow Interrupt, enable the interrupt TOF when FRC reach $FFFF.
• Bit 3 (RW) : Enable Output Compare Interrupt, enable the interrupt OCF when FRC reach the value of OCR.
• Bit 4 (RW) : Enable Input Capture Interrupt, enable the interrupt ICF when the FRC is catched in the ICR.
• Bit 5 (RO) : Timer Overflow Flag, is set to 1 when the FRC reach $FFFF, and is set to 0 when the TCSR is read.
• Bit 6 (RO) : Output Compare Flag, is set to 1 when the FRC reach the value of OCR, and is set to 0 when the TCSR is read and then a value is written in the OCR.
• Bit 7 (RO) : Input Capture Flag, is set to 1 when the ICR catch the FRC, and is set to 0 when TCS then ICR are read.

4 - RAM CONTROL

This register control the internal RAM:

• Bit 6 (RW) : enable internal RAM
• Bit 7 (RW) : if set to 1, stay at 1 until vcc-standby is down.

5 - KEYBOARD HANDLING

5.1 - Reading a key state

• Set DDR1 to input (%00000000)
• Set DDR3 & DDR4 to output (%11111111)
• Set all bit of DR3 & DR4 to 1, except for the row wich contains the key you want to read.
• Read DR1, look for the line wich contains the key you want to read, 0 mean the key is down, 1 mean the key is up.

5.2 - keyboard map

6301 Registers

The Hitachi 6301 is made of 7 registers :

• A : 8 bits register
• B : 8 bits register
• D : 16 bits register : A(hi) + B(low)
• X : 16 bits index register
• S : 16 bits stack register
• PC : 16 bits program counter register
• SR : 8 bits status register

The SR register:

• Bit 0 : Carry
• Bit 1 : oVerflow
• Bit 2 : Zero
• Bit 3 : Negative
• Bit 4 : Interrupt
• Bit 5 : Half Carry

6301 Addressing Modes

6301 Instruction Set Summary

Registers & Memory Instructions

Arithmetic Instructions

Logical Instructions

Shift & Rotate Instructions

Test & Compare Instructions

Status Register Instructions

Branching Instructions

Other Instructions

Additional Instructions (6301 only)

---